Which Of These Contains The Eip? Question 15 Options: Cpu Ram Control Unit Registers Alu
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Computer Architecture MCQs with answers
i. ___ is used to reduce cache hit fourth dimension.
A. Pseudo-associative caches
B. Avoiding address translation during cache indexing
C. Early restart and critical word get-go
D. Giving priority to read misses overwrites
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Answer: (B)
2. What does drive D or E symbolize?
A. Floppy drive
B. Hard disk
C. Second floppy bulldoze
D. CD-ROM drive
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Answer: (D)
3. The beginning of the architecture of the Itanium processor took place at ___.
A. Intel
B. Microsoft
C. Hewlett-Packard
D. Dell
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Answer: (C)
four. In the year 1834, Babbage attempted to build a digital computer, called ___.
A. IAS machine
B. Difference engine
C. Analytical engine
D. Pascaline
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Respond: (C)
v. In pipelining, the CPU executes each pedagogy in a series of post-obit stages: Education Fetching (IF) —–> Instruction Decoding (ID) —–> Education Execution (EX) —–>__ and Register Write back (WB).
A. Linear pipelines
B. Non-linear pipelines
C. Structural hazards
D. Memory admission (MEM)
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Answer: (D)
vi. The core element of parallel processing is ___.
A. Data sequencing.
B. CPU'south
C. Didactics execution
D. Printer
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Answer: (B)
seven. Ease-of-utilise and extensive graphic capabilities are the important characteristics of ___.
A. Servers
B. Desktop computers
C. Minicomputers
D. Micro-computers
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Reply: (B)
eight. ___ is a memory-memory vector machine that fetches vectors directly from retentivity to load the pipelines equally well as stores the pipeline outcomes straight to memory.
A. CCF Cyber 205
B. CCD Cyber 205
C. CDC Cyber 205
D. CFC Cyber 205
Respond: (C)
9. Fine-grain threading is considered equally a ___ threading.
A. Instruction-level
B. Loop level
C. Task-level
D. Function-level
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Answer: (A)
10. Ascertain Mapping Procedure?
A. Information technology is a procedure of transforming information from principal memory to cache retention.
B. It is a process that signifies the validity of the locality of reference.
C. Information technology is a procedure, which translates the principal retention accost to the cache retentivity address.
D. It is a process of detecting a give-and-take in the enshroud.
Respond: (A)
11. ___ is the logical construction of a computer'south Random-Admission Memory (RAM).
A. Retention addressing
B. Operation field
C. Address field
D. Addressing mode
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Answer: (A)
12. ___ the pipeline solution is considered attractive due to its simplicity for hardware and software.
A. Instruction count – 0xFF01
B. Flush
C. Load-stall count – 0xFF02
D. Plan counter
Evidence Answer Hibernate Answer
Respond: (B)
13. In dynamic scheduling, the hardware ___ the teaching execution to reduce stalling of the pipeline.
A. Rearranges
B. Bypasses
C. Forwards
D. Unhide
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Answer: (A)
14. The ALU performs the indicated operation on the operands prepared in the prior cycle and store the event in the specified destination operand location.
A. Fetch instruction
B. Decode instruction
C. Execute instruction
D. Fetch operand
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Answer: (C)
15. ___ states that "the performance improvement to be gained from using some faster fashion of execution is limited by the fraction of the time the faster mode can be used."
A. Principle of the locality
B. Hybrid technique
C. Variable-length technique
D. Amdahl's Law
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Respond: (D)
sixteen. ___ is an performance that fetches the non-zero elements of a sparse vector from memory.
A. Strip mining
B. ETA-10
C. Scatter
D. Get together
Answer: (D)
17. ___ execution is the temporal behaviour of the N-client 1-server model where one client is served at whatsoever given moment.
A. Unmarried data
B. Concurrent
C. Parallel
D. Multiple data
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Respond: (B)
18. In which command, the interface responds by transmitting information?
A. Data input
B. Status
C. Data output
D. Control
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Answer: (C)
19. Registers that are maintained by some of the processors for recording the condition of arithmetics, as well as logical operations, are called ___.
A. Condition code registers
B. Not-condition code registers
C. Re-locatable code
D. Branch registers
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Respond: (A)
20. ___ mapping is used in cache organisation which is the quickest and most supple organisation.
A. set associative
B. Directly
C. Sequential
D. Associative
Respond: (D)
21. The high-level attributes of a reckoner'southward architecture, such equally the memory system, the retention integration, and the architecture of the internal processor or CPU, are components of the term ___.
A. Organisation
B. Hardware
C. Software
D. Educational activity gear up
Answer: (A)
22. The smallest unit of memory that the CPU can read or write is ___.
A. Word
B. Mode
C. Cell
D. Field
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Respond: (C)
23. In which of the following cases, any completing instruction may not exist permitted to write its result?
A. One of the operands is the same as the upshot of the completing instruction
B. Being of any instruction which has read its operand
C. Operands that do not have the aforementioned annals every bit destination
D. If the scoreboard has not detected any WAR hazard
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Answer: (A)
24. ___ is collecting the group of data elements distributed in memory and subsequently that placing them in linear sequential register files.
A. Vectorisation
B. Pipelining
C. Retentiveness
D. Vector register
Answer: (A)
25. The configuration, in which no difference between memory and I/O devices is seen by the CPU, is referred to as ___.
A. Memory unit of measurement
B. Memory-mapped I/O
C. Retentivity address annals
D. Memory unit
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Answer: (B)
26. ___ address of the operand calculated during the prior bicycle is used to access memory.
A. Memory access completion cycle
B. Teaching decode fetch cycle
C. Instruction fetch wheel
D. Retentivity access fetch bicycle
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Answer: (A)
27. A normal CPU operates on ___.
A. Multiple scalars
B. Multiple vectors
C. Vector
D. One scalar at a time
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Answer: (D)
28. How many singled-out functional units are present in CDC6600?
A. 16
B. vii
C. 5
D. 4
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Answer: (A)
29. The fourth generation of computers (1978-till date) was marked by the utilise of ___.
A. Integrated Circuits
B. Large-Calibration Integrated (LSI) circuits
C. Transistors
D. Vacuum Tubes
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Answer: (B)
30. ___ occurs when an instruction depends on the result of previous instruction in a mode that is exposed by the overlapping of instructions in the pipeline.
A. Information hazards
B. Control hazards
C. Structural hazards
D. Risk in the pipeline
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Respond: (A)
31. In ___ each address field determines two address fields i.e. either a retentiveness give-and-take or the processor register.
A. Naught-address instructions
B. 2-address instructions
C. One-address instructions
D. Three-accost instructions
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Answer: (B)
32. What was used to shop a small number of bytes of data?
A. RAM
B. Disks
C. Punch cards
D. Tape drives
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Answer: (C)
33. The scalar registers are likewise linked to the functional units with the help of the pair of ___.
A. Crossbars
B. Vertical bars
C. Horizontal bars
D. Straight bars
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Answer: (A)
34. ___ must be able to deal with both annals and memory operands as well as destinations.
A. CISC pipelines
B. RISC pipelines
C. Load/Store by-passing
D. Branch instructions
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Answer: (A)
35. ___ design separates the testing for condition as well as branching. Information technology is followed by Pentium which makes employ of the flag register for recording the outcome of the test condition.
A. Test-and-jump
B. Status lawmaking register
C. Set-and then-jump
D. PC-relative
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Answer: (C)
36. In ___ operation a vector moves from memory to vector register.
A. Integer performance
B. Logical operation
C. Load vector functioning
D. Store vector functioning
Answer: (C)
37. Which office can fetch and issue instructions from a queue or latch?
A. IF
B. DLX
C. ID
D. EX
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Answer: (A)
38. ___ consists of a diversity of expert instruction and may just not be frequently used in practical programs.
A. Complex pedagogy set calculator
B. Reduced educational activity prepare computer
C. Very long didactics word
D. Very brusque instruction give-and-take
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Answer: (A)
39. The term RISC stands for ___.
A. Random Education Set Computing
B. Register Educational activity Set Computing
C. Reduced Instruction Set Computing
D. Reduced Teaching Set Compiler
Answer: (D)
40. For using the ___ technique, the compiler should have the entire knowledge of the arrangement and its timings.
A. Pre-fetching
B. Non-blocking writes
C. Multithreading
D. Awarding of cache memory
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Answer: (A)
41. ___ in a dataflow graph represents data paths.
A. Nodes
B. Sticky tokens
C. Edges
D. Data links
Evidence Answer Hibernate Answer
Answer: (C)
42. CPA stands for ___.
A. Acquit-processor adder
B. Carry-propagation adder
C. Complex-procedure application
D. Computer-propagation adder
Answer: (B)
43. Consider the design aspects of a CM5 system with 32 processors and land which of the beneath options is truthful?
A. Retentiveness of 32 Gbyte
B. 128 information paths
C. iii.0 synchronisation time
D. Peak speed of 128
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Respond: (B)
44. ___ units are generally floating-signal units that are completely pipelined.
A. Scalar registers
B. Vector load and shop unit
C. Vector functional unit
D. Control unit of measurement
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Answer: (C)
45. Which is the simplest scheme to handle branches?
A. Freeze or Flush the pipeline
B. Assume each branch as not-taken
C. Predict-not-taken or predict-untaken scheme
D. Assume each branch every bit taken
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Answer: (A)
46. It deals with the outcome of pick of hardware components and interconnecting them to create computers that achieve specified functional, performance, and cost goals.
A. Von-Neumann Architecture
B. Computational Model
C. Execution Model
D. Computer Architecture
Answer: (D)
47. In this mode, the instruction specifies a register in the CPU that contains the accost of the operand and not the operand itself.
A. Register Indirect Fashion
B. Auto-increment or Auto-decrement Mode
C. Register Mode
D. Immediate Way
Reply: (A)
48. Layout and ___ are the two aspects of branch processing.
A. Treatment of unresolved conditional branches
B. Accessing the branch target path
C. Branch detection
D. Micro-architectural implementation
Answer: (D)
49. Which of the following storage devices crave constant electricity?
A. Hard drive
B. Disks
C. Tape drive
D. RAM
Answer: (D)
l. ___ is used to reduce cache hit fourth dimension.
A. Giving priority to read misses overwrites
B. Early on restart and critical discussion beginning
C. Fugitive address translation during cache indexing
D. Pseudo-associative caches
Prove Respond Hide Answer
Reply: (C)
51. The equation of average retentiveness access time = Hit time + ___ ten ___.
A. Miss charge per unit, Miss penalty
B. Miss penalty, Cache size
C. Miss penalty, Hitting time
D. Enshroud size, Miss penalization
Reply: (A)
52. 1. ___ is a annals that temporarily stores the data that is to be written in the memory or the information received from the memory.
2. ___ identifies the accost of memory location from where the information or instruction is to exist accessed or where the data is to exist stored.
A. Retentivity Accost Register, Instruction Register
B. Memory Buffer Register, Retention Address Register
C. Memory Accost Annals, Memory Buffer Register
D. Instruction Annals, Memory Address Register
Respond: (C)
53. 1. The ___ should be checked for correctness.
2. ___ means either store can bypass loads or vice versa, without violating the memory data dependencies.
A. Reorder buffer, Load, and store reordering
B. Processor consistency, Reorder buffer
C. Speculative loads, Load/Store bypassing
D. Memory consistency, LMD
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Respond: (C)
54. 1. In the belatedly 1970s, nosotros observed the emergence of ___ that were high-performance computers for scientific computing.
ii. In the 1960s, the ___ used to exist the most prevalent i.
A. Main-frame computers, Microcomputers
B. Supercomputers, Main-frame computers
C. Microcomputers, Supercomputers
D. Processors, Microprocessors
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Answer: (B)
55. Consider the following statements with respect to RAIDS:
1. BIP is an acronym for Block-interleaved parity and is equivalent to RAID three.
ii. Magnetic disks help provide information when the disk fails equally the data is recorded in each sector that helps discover errors.
Country True or Imitation:
A. one- Simulated, 2- False
B. 1- True, 2- True
C. 1- False, 2- True
D. 1- True, 2- Simulated
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Respond: (C)
56. 1. In pipelining, two or more instructions that are independent of each other tin overlap. This possibility of overlap is known as ___.
two. In the example of DLX (DLX is a RISC processor architecture) pipeline, the structural & data hazards are examined during the ___.
A. Instruction level parallelism, Instruction decode
B. Floating-point registers, Structural hazards
C. Structural hazards, Data gamble
D. Instruction decode, Educational activity level parallelism
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Respond: (A)
57. Consider the following statements with respect to MPP:
1. If a fault occurs during ciphering, the sequence of instructions following the terminal dump to local retentiveness must exist repeated afterward the replacement of the fault-containing column.
2. The processing elements are linked by a 2-dimension well-nigh-neighbor mesh and this gives an reward of loftier bandwidth.
Land True or Fake:
A. 1- False, 2- False
B. one- True, 2- True
C. 1- False, 2- Truthful
D. 1- True, two- Imitation
Respond: (C)
58. 1. A mutual foundation or epitome that links the reckoner builder
2. The ___ operates by manipulating symbols on a record.
A. Computational model, Turing automobile architecture
B. Turing automobile compages, Computational Model
C. Von-Neumann architecture, Dataflow architecture
D. Turing auto architecture, Von-Neumann architecture
Show Answer Hibernate Answer
Answer: (A)
59. Consider the following statements with respect to information hazards:
1. In pipelining, the control hazards ascend when the sequence of reading/writing accesses to operands.
2. Pipelining has a major effect on irresolute the relative timing of instructions by executing them at the same fourth dimension. This leads to data and command hazards.
State True or False:
A. ane- Truthful, 2- True
B. 1- False, 2- True
C. 1- Truthful, ii- False
D. 1- False, 2- Fake
Evidence Answer Hide Respond
Answer: (B)
lx. Consider the following statements with respect to instructions for control flow:
ane. In a program control blazon of instruction, execution of the education may alter the address value in the plan counter and cause the menses of control to be altered.
2. In one case a information transfer or information manipulation pedagogy is executed, control returns to the decode wheel with the programme counter containing the accost of the didactics next in sequence.
State True or False:
A. 1- True, 2- True
B. 1- False, 2- Fake
C. 1- False, 2- True
D. one- True, 2- False
Answer: (D)
61. 1. ___ is the system with multiple CPUs, which are capable of independently executing unlike tasks in parallel.
two. In this category every processor and retentiveness module has a like admission time.
A. Multiprocessor, UMA
B. UMA, Microprocessor
C. Microprocessor, Multiprocessor
D. UMA, NUMA
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Answer: (A)
62. The Cray-1usually had a performance of most ___, but with upwardly to three chains running, information technology could hit the highest signal at ___.
A. 80 MFLOPS, 140 MFLOPS
B. 80 MFLOPS, 120 MFLOPS
C. 80 MFLOPS, 240 MFLOPS
D. 120 MFLOPS, 240 MFLOPS
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Answer: (C)
63. Consider the below-mentioned statements with respect to virtual address manner.
1. In the virtual accost way, cache admission efficiency is faster than the physical addressing fashion.
2. In the virtual address fashion, cache lookup is delayed.
State Truthful or False:
A. 1- True, 2- Simulated
B. one- True, 2- True
C. ane- False, 2- False
D. 1- False, 2- True
Evidence Reply Hibernate Answer
Answer: (D)
64. 1. ___ executes only the instructions that are commonly used in programs and thus, makes the process simpler.
two. ___ consists of a variety of expert instructions and may just not exist frequently used in applied programs.
A. Complex instruction set reckoner (CISC), Very long instruction give-and-take (VLIW)
B. Reduced educational activity set computer (RISC), Complex instruction set computer (CISC)
C. Reduced instruction set computer (RISC), Very long instruction word (VLIW)
D. Very long educational activity word (VLIW), Reduced instruction gear up figurer (RISC)
Answer: (B)
65. Consider the below-mentioned statements with respect to the dataflow graph:
one. Dataflow graph is too chosen a flow dependency graph.
2. Dataflow graph is asynchronous as the execution of a node starts when matching data is available at a node's input ports.
State True or False:
A. i- Truthful, 2- True
B. 1- True, 2- False
C. 1- False, 2- True
D. i- False, ii- False
Show Respond Hide Answer
Answer: (C)
66. Consider the following statements with respect to the number of pipeline stages used to perform a given task:
one. Specification of the subtasks to be performed in only the first stage of the pipeline.
2. Layout of the stage sequence, i.e., whether the stages are used in a strictly sequential fashion or some stages are recycled.
State Truthful or False:
A. one- Truthful, 2- True
B. i- True, ii- Fake
C. 1- Simulated, 2- False
D. i- False, ii- True
Answer: (D)
67. one. ___ is a method that is basically utilized for handling the problems related to the co-operative.
2. ___ helps in instruction execution. It receives branch instructions and resolves the conditional branches as early as possible.
A. Branch processing, Intel IA-64 compages
B. Branch prediction, Co-operative processing
C. Intel IA-64 architecture, RISC
D. PC register, Branch prediction
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Answer: (B)
68. one. ___ occur from resource conflicts when the hardware cannot back up all possible combinations of instructions in simultaneous overlapped execution.
ii. ___ occurs when an instruction depends on the effect of previous teaching in a way that is exposed by the overlapping of instructions in the pipeline.
A. Structural hazards, Data hazards
B. Command hazards, Structural hazards
C. Enshroud miss, Hazard in the pipeline
D. Control hazards, Cache miss
Show Reply Hibernate Answer
Answer: (A)
69. Consider the following statements with respect to parallelism in pipelining:
ane. When two or more than instructions that are independent of each other, overlap, they are called Dynamic Scheduling.
2. Directly line parallelism is always greater than loop level parallelism.
State Truthful or Faux:
A. i- True, 2- True
B. 1- True, 2- False
C. i- Faux, two- False
D. 1- False, 2- True
Show Reply Hide Respond
Answer: (C)
70. Consider the following statements with respect to I/O performance measures:
ane. Throughput is the average number of tasks completed by the server over a period of fourth dimension.
two. The two well-nigh common measures of I/O operation, used currently, are throughput and response fourth dimension.
State True or Imitation:
A. 1- True, 2- True
B. 1- Fake, two- False
C. one- True, 2- False
D. one- False, 2- True
Testify Respond Hibernate Answer
Answer: (C)
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Which Of These Contains The Eip? Question 15 Options: Cpu Ram Control Unit Registers Alu,
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